The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Jan. 24, 2015
Synopsys, Inc., Mountain View, CA (US);
Ankush Oberai, Fremont, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A layout design for a semiconductor chip includes two or more layers, each including a set of shapes, which are used for various fabrication processes during the manufacture of a physical semiconductor chip. Some manufacturing processes create physical features on the semiconductor chip that do not directly correspond to shapes in the layout design. To facilitate design analysis of such semiconductor chips, shapes from the layout design are selected and manipulated by performing one or more operations, such as Boolean operations, on the shapes to generate new shapes. The new shapes, which can represent physical features of the manufactured semiconductor chip, are then displayed, along with an image of the corresponding section of the physical semiconductor chip, to facilitate design analysis, such as failure analysis.