The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Dec. 26, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Prahladachar Jayaprakash Bharadwaj, Bangalore, IN;

Debendra Das Sharma, Saratoga, CA (US);

Harshit Poladia, San Jose, CA (US);

Kanaka Lakshmi Gadey Naga Venkata, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3253 (2013.01); G06F 13/4027 (2013.01);
Abstract

A method of staggering lanes in a peripheral component interconnect express (PCI-Express) port is described herein. The method includes initiating the port to enter or exit an electrical idle state. The method also includes forwarding a token to a predetermined lane of the port. Additionally, the method includes turning the predetermined lane ON or OFF by indication to an analog circuit interface. The method also includes forwarding the token to a neighboring lane when a staggering interval timer elapses.


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