Non-planar field effect transistor test structure and lateral dielectric breakdown testing method

Abstract

Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.