The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Oct. 08, 2015
Applicant:

Inotera Memories, Inc., Taoyuan, TW;

Inventors:

Shing-Yih Shih, New Taipei, TW;

Neng-Tai Shih, New Taipei, TW;

Assignee:

INOTERA MEMORIES, INC., Taoyuan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/28 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/49811 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A package-on-package (PoP) assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side, at least one chip mounted on the first side within a chip mounting area through a plurality of bumps, a molding compound disposed on the first side, the molding compound covering the at least one chip, and a plurality of peripheral bump structures penetrating through the molding compound within the peripheral area. Each of the peripheral bump structures includes conductive pillar and a partial TMV directly stacked on the conductive pillar. A plurality of solder balls is mounted on the second side of the interposer. The top die package is electrically connected to the peripheral bump structures.


Find Patent Forward Citations

Loading…