The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Jul. 16, 2015
Sts Semiconductor & Telecommunications Co., Ltd., Cheonan-si, Chungcheongnam-do, KR;
Abstract
Provided are a wafer level package and a manufacturing method thereof. The wafer level package method includes preparing a patterned wafer, forming a recess in a position, in which a semiconductor chip is to be attached, of the patterned wafer through an etching process, fixing the semiconductor chip to the interior of the recess, and applying a passivation material to portions other than the semiconductor chip within the recess and to an upper end of the wafer. The wafer level package includes a silicon or glass wafer including a recess formed through etching and having an area larger than a semiconductor chip, a semiconductor chip fixed to the interior of the recess, and a passivation material filling an empty space other than the semiconductor chip within the recess and applied to a portion corresponding to an area larger than the semiconductor chip on an upper end of the wafer.