The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Jun. 12, 2015
Applicant:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Inventors:
Lei Fu, Austin, TX (US);
Frank Gottfried Kuechenmeister, Dresden, DE;
Michael Zhuoying Su, Round Rock, TX (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 25/07 (2006.01); H01L 23/498 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 25/0657 (2013.01); H01L 25/073 (2013.01); H01L 25/50 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/15311 (2013.01);
Abstract
Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.