The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Apr. 07, 2015
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Shu-Hsuan Lin, Hsinchu, TW;

Chia-Wei Wang, Taichung, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/418 (2006.01); G11C 7/12 (2006.01); G11C 11/417 (2006.01); G11C 29/02 (2006.01); G11C 11/41 (2006.01);
U.S. Cl.
CPC ...
G11C 11/418 (2013.01); G11C 7/12 (2013.01); G11C 11/417 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 11/41 (2013.01);
Abstract

A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.


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