The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Dec. 18, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

John H. Crawford, Saratoga, CA (US);

Brian S. Morris, Santa Clara, CA (US);

Sreenivas Mandava, Los Altos, CA (US);

Raj K. Ramanujan, Federal Way, WA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01); G11C 11/406 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/406 (2013.01); G06F 13/1636 (2013.01); G11C 7/02 (2013.01); G11C 11/40611 (2013.01);
Abstract

Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.


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