The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Aug. 05, 2014
Synopsys Taiwan Co., Ltd., Taipei, TW;
Yingtsai Chang, Fremont, CA (US);
Sweyyan Shei, Cupertino, CA (US);
Hung-Chun Chiu, Fremont, CA (US);
Meng-Chyi Lin, Toufen Township, TW;
Hwa Mao, Da-an District, TW;
Ming-Yang Wang, Lafayette, CA (US);
Yu-Chin Hsu, Cupertino, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.