IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9448950 B1

PDFFull Text
Date of Patent:
Sep. 20, 2016

Filed:

Dec. 24, 2013

Using authenticated manifests to enable external certification of multi-processor platforms

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vincent R. Scarlata, Beaverton, OR (US);

Simon P. Johnson, Beaverton, OR (US);

Vladimir Beker, Ariel, IL;

Jesse Walker, Portland, OR (US);

Carlos V. Rozas, Portland, OR (US);

Amy L. Santoni, Scottsdale, AZ (US);

Ittai Anati, Haifa, IL;

Raghunandan Makaram, Northborough, MA (US);

Francis X. McKeen, Portland, OR (US);

Uday R. Savagaonkar, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Lowenstein Sandler LLP

Primary Examiner:

Andrew Nalven

Assistant Examiner:

Courtney Fields

Int. Cl.
CPC ...
G06F 21/00 (2013.01); H04L 29/06 (2006.01); G06F 12/14 (2006.01); G06F 21/74 (2013.01); H04L 9/32 (2006.01); H04L 12/24 (2006.01); G06F 21/62 (2013.01); G06F 21/57 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1466 (2013.01); G06F 21/74 (2013.01); G06F 2212/1052 (2013.01);
Abstract

Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a plurality of processing devices communicatively coupled to the architecturally protected memory, each processing device comprising a first processing logic to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory, or preventing an unauthorized access to the architecturally protected memory; wherein each processing device further comprises a second processing logic to establish a secure communication channel with a second processing device of the processing system, employ the secure communication channel to synchronize a platform identity key representing the processing system, and transmit a platform manifest comprising the platform identity key to a certification system.

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