The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Dec. 22, 2011
Theodros Yigzaw, Sherwood, OR (US);
Oded Lempel, Amikam, IL;
Hisham Shafi, Akko, IL;
Geeyarpuram N. Santhanakrishnan, Mercer Island, WA (US);
Jose A. Vargas, Rescue, CA (US);
Ganapati N Srinivasa, Portland, OR (US);
Mohan J Kumar, Aloha, OR (US);
Larisa Novakovsky, Haifa, IL;
Lihu Rappoport, Haifa, IL;
Chen Koren, Folsom, AS (US);
Julius Mandelblat, Haifa, IL;
Michael Mishaeli, Zichron Yaakov, IL;
Theodros Yigzaw, Sherwood, OR (US);
Oded Lempel, Amikam, IL;
Hisham Shafi, Akko, IL;
Geeyarpuram N. Santhanakrishnan, Mercer Island, WA (US);
Jose A. Vargas, Rescue, CA (US);
Ganapati N Srinivasa, Portland, OR (US);
Mohan J Kumar, Aloha, OR (US);
Larisa Novakovsky, Haifa, IL;
Lihu Rappoport, Haifa, IL;
Chen Koren, Folsom, AS (US);
Julius Mandelblat, Haifa, IL;
Michael Mishaeli, Zichron Yaakov, IL;
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.