The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Jan. 12, 2015
Applicants:
Peter J. Kuhn, Austin, TX (US);
Feng Zhou, Austin, TX (US);
Inventors:
Peter J. Kuhn, Austin, TX (US);
Feng Zhou, Austin, TX (US);
Assignee:
Freescale Semiconductor, Inc, Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 45/00 (2006.01); G11C 29/00 (2006.01); G11C 29/02 (2006.01); G11C 13/00 (2006.01); G11C 29/04 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1641 (2013.01); G11C 13/0007 (2013.01); G11C 13/0021 (2013.01); G11C 13/0069 (2013.01); G11C 29/006 (2013.01); G11C 29/028 (2013.01); G11C 29/04 (2013.01); H01L 27/2463 (2013.01); G11C 2013/0083 (2013.01); G11C 2013/0088 (2013.01); G11C 2029/0403 (2013.01);
Abstract
A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.