The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Aug. 13, 2013
Applicant:

Commissariat À L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Frédéric Allibert, Albany, NY (US);

Maud Vinet, Albany, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 27/085 (2006.01); H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0696 (2013.01); G06F 17/5081 (2013.01); H01L 21/823412 (2013.01); H01L 27/0207 (2013.01); H01L 27/085 (2013.01); H01L 27/11 (2013.01); H01L 27/1203 (2013.01);
Abstract

The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor () of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor () of the other transistor of said transistor pair by a distance D less than half the transistor channel width, said distance d between two sub-transistors () being measured between the respective center of the channels of said sub-transistors.


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