The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Jan. 08, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Peter Baars, Dresden, DE;

Hans-Peter Moll, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 49/02 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/308 (2013.01); H01L 21/3212 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 27/0629 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/495 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.


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