The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Jul. 31, 2013
Applicants:

Mehul D. Shroff, Austin, TX (US);

Douglas M. Reber, Austin, TX (US);

Edward O. Travis, Austin, TX (US);

Inventors:

Mehul D. Shroff, Austin, TX (US);

Douglas M. Reber, Austin, TX (US);

Edward O. Travis, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/768 (2013.01); H01L 23/5329 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface.


Find Patent Forward Citations

Shroff, Mehul. (2016). Capping layer interface interruption for stress migration mitigation (U.S. Patent No. 9443804). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9443804

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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