The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Jul. 16, 2015
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Chi Ho Leung, Kwun Tong, HK;

Ke Xue, Kwai Chung, HK;

Soenke Habenicht, Hamburg, DE;

Wai Hung William Hor, Tsuen Wan, HK;

San Ming Chan, Tsuen Wan, HK;

Wai Keung Ng, Tuen Mun, HK;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4952 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/49541 (2013.01); H01L 23/49582 (2013.01); H01L 24/85 (2013.01); H01L 24/97 (2013.01); H01L 23/3121 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/97 (2013.01); H01L 2924/19107 (2013.01);
Abstract

A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure.


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