The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Jun. 07, 2013
Applicant:

Globalfoundries U.s. 2 Llc, Hopewell Junction, NY (US);

Inventors:

Hyun-Jin Cho, Guilderland, NY (US);

Tenko Yamashita, Schenectady, NY (US);

Chun-chen Yeh, Clifton, NY (US);

Hui Zang, Albany, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); H01L 22/34 (2013.01); H01L 22/12 (2013.01);
Abstract

Disclosed is a novel system and method to form local interconnects in a continuity test structure. The method begins with a first set of transistor gate lines and a second set of transistor gate lines are formed. Next, a first group of two or more local interconnect lines landing on transistor gates and formed substantially perpendicular to the first set of transistor gate lines and electrically coupled therewith is formed using a first lithography pass. A second group of two or more local interconnect lines landing and formed substantially perpendicular to the second set of transistor gate lines and electrically coupled therewith is formed during second lithography pass. For some technologies, a third set of transistor gate lines is formed along with a third group using a third lithography pass.


Find Patent Forward Citations

Loading…