The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Mar. 13, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kun-Ju Li, Tainan, TW;

Po-Cheng Huang, Kaohsiung, TW;

Yu-Ting Li, Chiayi, TW;

Jen-Chieh Lin, Kaohsiung, TW;

Chih-Hsun Lin, Ping-Tung County, TW;

Tzu-Hsiang Hung, Kaohsiung, TW;

Wu-Sian Sie, Tainan, TW;

I-Lun Hung, Kaohsiung, TW;

Wen-Chin Lin, Tainan, TW;

Chun-Tsen Lu, Tainan, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/321 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02362 (2013.01); H01L 21/02271 (2013.01); H01L 21/02354 (2013.01); H01L 21/324 (2013.01); H01L 21/3212 (2013.01); H01L 22/12 (2013.01);
Abstract

A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.


Find Patent Forward Citations

Loading…