The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Dec. 10, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gilbert Neiger, Portland, OR (US);

Rajesh Sankaran Madukkarumukumana, Portland, OR (US);

Richard A. Uhlig, Hillsboro, OR (US);

Udo Steinberg, Sohland a.d.Spree, DE;

Sebastian Schoenberg, Hillsboro, OR (US);

Sridhar Muthrasanallur, Bangalore, IN;

Steven M. Bennett, Hillsboro, OR (US);

Andrew V. Anderson, Forest Grove, OR (US);

Erik C. Cota-Robles, Mountain View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2006.01); G06F 9/46 (2006.01); G06F 13/24 (2006.01); G06F 13/26 (2006.01); G06F 3/00 (2006.01); G06F 13/00 (2006.01); G06F 9/455 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 13/24 (2013.01); G06F 9/45533 (2013.01); G06F 9/4812 (2013.01);
Abstract

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.


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