The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Dec. 29, 2012
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
David Keppel, Seattle, WA (US);
Kelvin Kwan, Santa Clara, CA (US);
Jawad Nasrullah, Palo Alto, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2016.01); G06F 12/08 (2016.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0804 (2013.01); G06F 1/3243 (2013.01); G06F 1/3275 (2013.01); G06F 12/121 (2013.01); G06F 12/122 (2013.01); G06F 2212/1028 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1239 (2013.01);
Abstract
A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.
Quick Actions:
Keppel, David. (2016). Apparatus and method for reduced core entry into a power state having a powered down core cache (U.S. Patent No. 9442849). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9442849
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile