The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Feb. 04, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jiann-Tyng Tzeng, Hsinchu, TW;

Meng-Hung Shen, Zhubei, TW;

Yi-Feng Chen, Xinpu Township, TW;

Charles Chew-Yuen Young, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 1/12 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); H03K 19/20 (2013.01);
Abstract

A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal.


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