The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Sep. 24, 2009
Applicants:

Atsushi Fukushima, Ibaraki, JP;

Yuichiro Shindo, Ibaraki, JP;

Susumu Shimamoto, Ibaraki, JP;

Inventors:

Atsushi Fukushima, Ibaraki, JP;

Yuichiro Shindo, Ibaraki, JP;

Susumu Shimamoto, Ibaraki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C22C 9/00 (2006.01); C23C 14/34 (2006.01); C23C 14/18 (2006.01); C23C 14/56 (2006.01);
U.S. Cl.
CPC ...
C23C 14/3414 (2013.01); C22C 9/00 (2013.01); C23C 14/185 (2013.01); C23C 14/564 (2013.01);
Abstract

Provided is a high-purity copper or high-purity copper alloy sputtering target of which the purity is 6N or higher and in which the content of the respective components of P, S, O and C is 1 ppm or less, wherein the number of nonmetal inclusions having a particle size of 0.5 μm or more and 20 μm or less is 30,000 inclusions/g or less. As a result of using high-purity copper or high-purity copper alloy from which harmful inclusions of P, S, C and O system have been reduced as the raw material and controlling the existence form of nonmetal inclusions, the present invention addresses a reduction in the percent defect of wirings of semiconductor device formed by sputtering a high-purity copper target so as to ensure favorable repeatability.


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