The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2016
Filed:
Dec. 22, 2011
Harish K. Krishnamurthy, Hillsboro, OR (US);
Annabelle Pratt, Littleton, CO (US);
Mark L. Neidengard, Beaverton, OR (US);
George E. Matthew, Hillsboro, OR (US);
James Alexander Darnes, Oxfordshire, GB;
Harish K. Krishnamurthy, Hillsboro, OR (US);
Annabelle Pratt, Littleton, CO (US);
Mark L. Neidengard, Beaverton, OR (US);
George E. Matthew, Hillsboro, OR (US);
James Alexander Darnes, Oxfordshire, GB;
Intel Corporation, Santa Clara, CA (US);
Abstract
Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers.