The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Feb. 08, 2016
Applicant:

Semileds Optoelectronics Co., Ltd., Chu-Nan, CN;

Inventor:

Yi-Feng Shih, Chu-Nan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 33/62 (2010.01); H01L 33/06 (2010.01); H01L 33/10 (2010.01); H01L 33/32 (2010.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 33/007 (2013.01); H01L 33/06 (2013.01); H01L 33/10 (2013.01); H01L 33/32 (2013.01); H01L 2933/0066 (2013.01);
Abstract

A method for fabricating a flip chip light emitting diode (FCLED) die includes forming an epitaxial stack on a carrier substrate having an n-type confinement layer, a multiple quantum well (MQW) layer, and a p-type confinement layer, forming a mirror layer on the p-type confinement layer, forming an n-trench in the n-type confinement layer, forming an n-conductor layer in the n-trench on the n-type confinement layer, forming a p-metal layer on the p-type confinement layer, forming a first electrical isolator layer on the n-conductor layer and a second electrical isolator layer on the p-metal layer, forming a p-pad on the first electrical isolator layer, and forming an n-pad the second electrical isolator layer.


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