The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Dec. 10, 2015
Applicant:

Nantong Fujitsu Microelectronics Co., Ltd., Nantong, CN;

Inventor:

Jiangen Shi, Nantong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/31 (2006.01); H01L 21/82 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/563 (2013.01); H01L 21/76885 (2013.01); H01L 21/82 (2013.01); H01L 23/3107 (2013.01); H01L 23/53228 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01);
Abstract

A method for wafer-level packaging includes providing a semiconductor wafer having a plurality of semiconductor chips connected by connection stems in the wafer. The method further includes forming a plurality of through holes in the connections stems; forming a protective layer covering the wafer with a plurality of positions for planting soldering balls exposed. The protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers formed in the through holes. The upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers. The method also includes forming soldering balls on the positions for planting soldering balls and finally, forming a plurality of packaged individual semiconductor chip structures by cutting the wafer along the connection stems with the through holes.


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Shi, Jiangen. (2016). Method and structure for wafer-level packaging (U.S. Patent No. 9437511). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9437511

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