The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Aug. 25, 2015
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chu-Yung Liu, Hsinchu, TW;

Hsing-Wen Chang, Hsinchu, TW;

Yao-Wen Chang, Hsinchu, TW;

Tao-Cheng Lu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/3459 (2013.01);
Abstract

A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.


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