The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Mar. 15, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yun He, Santa Clara, CA (US);

Narender R. Nagulapally, Folsom, CA (US);

Sanjib Sarkar, Folsom, CA (US);

Ivan Herrera Mejia, Folsom, CA (US);

Ruchira K. Liyanage, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/26 (2006.01); G06F 11/07 (2006.01); G06F 1/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/3253 (2013.01); G06F 11/0706 (2013.01); G06F 11/0754 (2013.01); G06F 11/0793 (2013.01); G06F 1/00 (2013.01); Y02B 60/1235 (2013.01);
Abstract

Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.


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