The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Jun. 01, 2012
Applicants:

Shi-wei Lee, Hong Kong, CN;

Rong Zhang, Hong Kong, CN;

Inventors:

Shi-Wei Lee, Hong Kong, CN;

Rong Zhang, Hong Kong, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 33/62 (2010.01); H01L 23/00 (2006.01); H01L 25/075 (2006.01); H01L 33/50 (2010.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 24/16 (2013.01); H01L 25/075 (2013.01); H01L 33/502 (2013.01); H01L 2224/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12041 (2013.01); H01L 2933/0033 (2013.01);
Abstract

A wafer having a plurality of light-emitting diode (LED) submounts and a method for fabricating an LED submount are provided. Each of the plurality of LED submounts of the wafer includes: a substrate (), including through vias (); an LED die () mounted in a cavity () on a first side of the substrate () and connected to the through vias (); a redistribution layer () attached to a second side of the substrate () connected to the LED die () through the through vias (). The method includes providing a wafer as a substrate (); providing a cavity () in the substrate () on a first side of the substrate (); providing through vias () in the substrate (), providing a redistribution layer () on the second side of the substrate (), and mounting an LED () in the cavity (), wherein the LED die () is connected to the redistribution layer () through the through vias ().


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