The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

May. 26, 2010
Applicants:

Robert Q. Xu, Fremont, CA (US);

Kuo-in Chen, Los Altos, CA (US);

Karl Lichtenberger, Sunnyvale, CA (US);

Sharon Shi, San Jose, CA (US);

Qufei Chen, San Jose, CA (US);

Kyle Terrill, Santa Clara, CA (US);

Inventors:

Robert Q. Xu, Fremont, CA (US);

Kuo-In Chen, Los Altos, CA (US);

Karl Lichtenberger, Sunnyvale, CA (US);

Sharon Shi, San Jose, CA (US);

Qufei Chen, San Jose, CA (US);

Kyle Terrill, Santa Clara, CA (US);

Assignee:

Vishay-Siliconix, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/792 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/66734 (2013.01); H01L 29/7811 (2013.01); H01L 21/26586 (2013.01); H01L 29/0638 (2013.01); H01L 29/407 (2013.01); H01L 29/42368 (2013.01);
Abstract

A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.


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