The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

May. 22, 2015
Applicants:

Imec Vzw, Leuven, BE;

Sony Corporation, Tokyo, JP;

Inventors:

Hideki Minari, Minato-ku, JP;

Shinichi Yoshida, Minato-ku, JP;

Geoffrey Pourtois, Villers-la-Ville, BE;

Matty Caymax, Leuven, BE;

Eddy Simoen, Ichtegem, BE;

Assignees:

IMEC VZW, Leuven, BE;

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/762 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02538 (2013.01); H01L 21/2855 (2013.01); H01L 21/28556 (2013.01); H01L 21/32051 (2013.01); H01L 21/32053 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/20 (2013.01); H01L 29/66522 (2013.01); H01L 29/7851 (2013.01); H01L 21/0262 (2013.01); H01L 21/02543 (2013.01); H01L 21/02546 (2013.01); H01L 21/02579 (2013.01);
Abstract

A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.


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