The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Sep. 05, 2014
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventors:

Haruo Nakazawa, Matsumoto, JP;

Masaaki Ogino, Matsumoto, JP;

Hidenao Kuribayashi, Matsumoto, JP;

Hideaki Teranishi, Hachioji, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/32 (2006.01); H01L 21/322 (2006.01); C30B 31/22 (2006.01); H01L 29/66 (2006.01); C30B 29/06 (2006.01); H01L 21/265 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3221 (2013.01); C30B 29/06 (2013.01); C30B 31/22 (2013.01); H01L 21/26513 (2013.01); H01L 21/3225 (2013.01); H01L 29/66325 (2013.01); H01L 29/66333 (2013.01);
Abstract

A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate.


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