The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2016
Filed:
Jul. 07, 2014
Synopsys, Inc., Mountain View, CA (US);
Ankush Oberai, Fremont, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
Defect characterization and failure analysis are useful tools for analyzing and improving fabrication for semiconductor chips. By using a layout and a netlist in combination with images of semiconductors, defects can be identified and analyzed. Electrical simulation can be performed on the netlist, based on the presence of the defect that was detected. Layout geometries where the defect was detected can be binned, and a search can be performed of the remainder of the layout for similar groupings of layout geometries. Various representations of the semiconductor can be cross-mapped, including layout, schematic, and netlist. The presence of certain defects can be correlated to yield, to performance, and to other characteristics.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile