The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Dec. 22, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sanjay Kumar, Hillsboro, OR (US);

Rajesh Sankaran, Portland, OR (US);

Subramanya Dulloor, Hillsboro, OR (US);

Sheng Li, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0671 (2013.01); G06F 2212/1032 (2013.01);
Abstract

A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.


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