The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

May. 21, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alain Gravel, Thousand Oaks, CA (US);

Robert G. Southworth, Chatsworth, CA (US);

Jonathan A. Dama, Encino, CA (US);

Ilango S. Ganga, Cupertino, CA (US);

Matthew J. Webb, Woodland Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/931 (2013.01); H04L 7/033 (2006.01); H04L 12/825 (2013.01); H04L 1/00 (2006.01); H04L 12/413 (2006.01);
U.S. Cl.
CPC ...
H04L 49/352 (2013.01); H04L 1/00 (2013.01); H04L 1/0002 (2013.01); H04L 7/033 (2013.01); H04L 7/0331 (2013.01); H04L 47/25 (2013.01); H04L 12/413 (2013.01);
Abstract

Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.


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