The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Jan. 18, 2013
Applicants:

Chin-shan Wang, Hsinchu, TW;

Jian-hong Lin, Yunlin, TW;

Chien-jung Wang, Hsinchu, TW;

Inventors:

Chin-Shan Wang, Hsinchu, TW;

Jian-Hong Lin, Yunlin, TW;

Chien-Jung Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/005 (2006.01); H01G 4/06 (2006.01); H01L 29/92 (2006.01); H01G 4/012 (2006.01); H01G 4/228 (2006.01); H01G 4/30 (2006.01); H01G 4/33 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/92 (2013.01); H01G 4/012 (2013.01); H01G 4/228 (2013.01); H01G 4/30 (2013.01); H01G 4/33 (2013.01); H01L 23/5222 (2013.01); H01L 28/60 (2013.01); H01L 28/86 (2013.01); H01L 28/90 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.


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