The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

Oct. 01, 2014
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yogesh Luthra, San Jose, CA (US);

Serguei Okhonin, Lausanne, CH;

Mikhail Nagoga, Lausanne, CH;

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); H01L 27/06 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01); G11C 7/00 (2006.01); H01L 29/73 (2006.01); H01L 29/732 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0664 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 7/00 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); H01L 29/732 (2013.01); H01L 29/7302 (2013.01); G11C 2211/4016 (2013.01);
Abstract

Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.


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