The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2016

Filed:

May. 24, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

You-Cheng Xiao, Taiping, TW;

Yen-Huei Chen, Jhudonog Township, TW;

Jung-Hsuan Chen, Hsin-Chu, TW;

Shao-Yu Chou, Chu-Pei, TW;

Li-Chun Tien, Tainan, TW;

Hung-Jen Liao, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/482 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/768 (2013.01); H01L 21/76832 (2013.01); H01L 23/485 (2013.01); H01L 23/4824 (2013.01); H01L 23/522 (2013.01); H01L 23/528 (2013.01); H01L 23/5286 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.


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