The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Jul. 15, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chan-Hong Chern, Palo Alto, CA (US);

Fu-Lung Hsueh, Cranbury, NJ (US);

Ming-Chieh Huang, San Jose, CA (US);

Bryan Sheffield, Austin, TX (US);

Chih-Chang Lin, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 19/0185 (2006.01); H03K 19/096 (2006.01); H03K 3/012 (2006.01); H03K 3/3562 (2006.01); H03K 3/356 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/01855 (2013.01); H03K 3/012 (2013.01); H03K 3/35625 (2013.01); H03K 3/356008 (2013.01); H03K 19/0016 (2013.01); H03K 19/0963 (2013.01);
Abstract

A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.


Find Patent Forward Citations

Chern, Chan-Hong. (2016). Circuit for reducing negative bias temperature instability (U.S. Patent No. 9419617). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9419617

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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