The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2016

Filed:

Dec. 19, 2013
Applicant:

Chengdu Monolithic Power Systems Co., Ltd., Chengdu, CN;

Inventors:

Rongyao Ma, Chengdu, CN;

Tiesheng Li, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0296 (2013.01); H01L 27/0255 (2013.01); H01L 29/4238 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/781 (2013.01); H01L 29/7808 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a termination area of the substrate and is electrically coupled between a source metal and a gate metal of the semiconductor device. The ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion. Such an ESD protection structure is beneficial to the formation of interlayer vias which are formed to couple the ESD protection structure to the source metal and the gate metal.


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