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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9418911 B1

PDFFull Text
Date of Patent:
Aug. 16, 2016

Filed:

Oct. 28, 2015

Three-dimensional semiconductor memory device having sidewall and interlayer molds

Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Jae-Joo Shim, Suwon-Si, KR;

Hansoo Kim, Suwon-Si, KR;

Wonseok Cho, Suwon-Si, KR;

Jaehoon Jang, Seongnam-Si, KR;

Woojin Cho, Yongin-Si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:

F. Chau & Associates, LLC

Primary Examiner:

Matthew Gordon

Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/31 (2006.01); H01L 27/115 (2006.01); H01L 21/768 (2006.01); H01L 23/29 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3157 (2013.01); H01L 21/76816 (2013.01); H01L 23/291 (2013.01); H01L 23/528 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01);
Abstract

Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

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