The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
Aug. 06, 2015
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Raghunandan Chaware, Sunnyvale, CA (US);
Inderjit Singh, Saratoga, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 23/00 (2006.01); H01L 23/053 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); H01L 23/053 (2013.01); H01L 23/3142 (2013.01); H01L 24/26 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/8385 (2013.01); H01L 2924/16196 (2013.01);
Abstract
A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is provided that includes an IC die, a package substrate and a lid. The IC die is coupled to the package substrate. The lid has a first surface and a second surface. The second surface of the lid faces away from the first surface and towards the IC die. The second surface of the lid has a plurality of engineered features. The adhesive couples the plurality of engineered features of the lid to the IC die.