The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
Aug. 03, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Mark B. Trobough, Olympia, WA (US);
Christopher S. Baldwin, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); G01R 1/04 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); G01R 1/0483 (2013.01); H01L 22/32 (2013.01); H01L 23/49838 (2013.01); H01L 2924/0002 (2013.01);
Abstract
In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
Trobough, Mark. (2016). Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates (U.S. Patent No. 9418906). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9418906
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile