The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2016
Filed:
Sep. 13, 2011
Sergey B. Gashkov, Moscow, RU;
Anatoli A. Bolotov, San Jose, CA (US);
Mikhail I. Grinchuk, San Jose, CA (US);
Lav D. Ivanovic, Sunnyvale, CA (US);
Anatoly A. Chasovshikh, Moscow, RU;
Alexei V. Galatenko, Moscow, RU;
Igor V. Kucherenko, Moscow, RU;
Sergey B. Gashkov, Moscow, RU;
Anatoli A. Bolotov, San Jose, CA (US);
Mikhail I. Grinchuk, San Jose, CA (US);
Lav D. Ivanovic, Sunnyvale, CA (US);
Anatoly A. Chasovshikh, Moscow, RU;
Alexei V. Galatenko, Moscow, RU;
Igor V. Kucherenko, Moscow, RU;
Intel Corporation, Santa Clara, CA (US);
Abstract
A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.