The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2016
Filed:
Jun. 25, 2015
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Chen-Hua Tsai, Hsinchu County, TW;
Rai-Min Huang, Taipei, TW;
Sheng-Huei Dai, Taitung County, TW;
Chun-Hsien Lin, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); H01L 29/1054 (2013.01); H01L 29/16 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7842 (2013.01); H01L 21/02647 (2013.01); H01L 21/2022 (2013.01); H01L 2029/7858 (2013.01);
Abstract
A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.