The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Oct. 15, 2014
Applicant:

Monolithic 3d Inc., San Jose, CA (US);

Inventors:

Zvi Or-Bach, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Israel Beinglass, Sunnyvale, CA (US);

Jan Lodewijk de Jong, Cupertino, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Zeev Wurman, Palo Alto, CA (US);

Assignee:

MONOLITHIC 3D INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/367 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); H01L 23/367 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 27/088 (2013.01);
Abstract

A semiconductor device, including: a first layer including first transistors, the first transistors are interconnected by at least one metal layer including copper or aluminum; a second layer including second transistors, the first layer is overlaid by the second layer, where the second layer includes a plurality of through layer vias having a diameter of less than 200 nm, where the second transistors include a source contact, the source contact including a silicide, and where the silicide has a sheet resistance of less than 15 ohm/sq.


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