The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Apr. 20, 2009
Applicants:

Mukta G. Farooq, Hopewell Junction, NY (US);

Robert Hannon, Wappingers Falls, NY (US);

Subramanian S. Iyer, Mount Kisco, NY (US);

Emily R. Kinser, Poughkeepsie, NY (US);

Inventors:

Mukta G. Farooq, Hopewell Junction, NY (US);

Robert Hannon, Wappingers Falls, NY (US);

Subramanian S. Iyer, Mount Kisco, NY (US);

Emily R. Kinser, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 24/92 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 24/06 (2013.01); H01L 24/80 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.


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