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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9406516 B1

PDFFull Text
Date of Patent:
Aug. 02, 2016

Filed:

Apr. 07, 2015

High-k metal gate process for lowering junction leakage and interface traps in nmos transistor

Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Jian-Cun Ke, Tainan, TW;

Chih-Wei Yang, Kaohsiung, TW;

Kun-Yuan Lo, Tainan, TW;

Chia-Fu Hsu, Tainan, TW;

Shao-Wei Wang, Taichung, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:

Winston Hsu

Scott Margo

Primary Examiner:

Truong Q Dang

Assistant Examiner:

Patricia Reddington

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 21/28194 (2013.01); H01L 21/28202 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 29/4966 (2013.01); H01L 29/518 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/7833 (2013.01); H01L 29/7834 (2013.01); H01L 29/165 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01);
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Find Patent Forward Citations

Ke, Jian-Cun. (2016). High-k metal gate process for lowering junction leakage and interface traps in nmos transistor (U.S. Patent No. 9406516). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9406516

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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