The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Jun. 27, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Baskaran Ganesan, Bangalore, IN;

Eric Dehaemer, Shrewsbury, MA (US);

Vinod Ambrose, Northborough, MA (US);

Harjinder Hullon, Santa Clara, CA (US);

Joseph Doucette, Waltha, MA (US);

Seow Fung Ooi, Gelugor, MY;

Min Huang, Cupertino, CA (US);

Zhiguo Wang, Palo Alto, CA (US);

Yin-Lung Lu, Hillsboro, OR (US);

William Johnson Bowhill, Framingham, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/3296 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1285 (2013.01);
Abstract

In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.


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