The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2016
Filed:
Jun. 09, 2011
Takuya Oga, Chiyoda-ku, JP;
Kazuyasu Sakamoto, Chiyoda-ku, JP;
Tsuyoshi Sugihara, Chiyoda-ku, JP;
Masaki Kato, Chiyoda-ku, JP;
Daisuke Nakashima, Chiyoda-ku, JP;
Tsuyoshi Jida, Chiyoda-ku, JP;
Gen Tada, Chiyoda-ku, JP;
Takuya Oga, Chiyoda-ku, JP;
Kazuyasu Sakamoto, Chiyoda-ku, JP;
Tsuyoshi Sugihara, Chiyoda-ku, JP;
Masaki Kato, Chiyoda-ku, JP;
Daisuke Nakashima, Chiyoda-ku, JP;
Tsuyoshi Jida, Chiyoda-ku, JP;
Gen Tada, Chiyoda-ku, JP;
Mitsubishi Electric Corporation, Tokyo, JP;
Abstract
A semiconductor device is provided, in which a first lead () is joined with the bottom electrode () of a MOS-FET () with first solder (), the top electrode () of the MOS-FET is joined with an internal lead () with second solder (), the internal lead is joined with a projection () of a second lead with third solder (), and the first lead, second lead, MOS-FET and internal lead are integrally molded using sealing resin (), wherein the first solder and second solder include support members () and (), respectively, located thereinside and positions of the internal lead and MOS-FET are stabilized by self-alignment.