The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

May. 19, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Jordan Plofsky, San Jose, CA (US);

Chooi Pei Lim, Bayan Lepas, MY;

Danny Biran, Cupertino, CA (US);

Francis Man-Chit Chow, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 9/00 (2006.01); H01L 21/283 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 21/283 (2013.01); H01L 21/78 (2013.01); H01L 23/544 (2013.01);
Abstract

A mask set is described. In one implementation, the mask set includes: a first plurality of base layer masks, where each base layer mask of the first plurality of base layer masks includes a plurality of base layer tiles of a first tile size; a first plurality of top layer masks, where each top layer mask of the first plurality of top layer masks includes a plurality of first top layer tiles of the first tile size; and a second plurality of top layer masks, where each top layer mask of the second plurality of top layer masks includes a plurality of second top layer tiles of a second tile size; where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described.


Find Patent Forward Citations

Loading…